Non-volatile memory devices have been developed by the semiconductor integrate circuit industry for various applications such as computers and digital communications. Examples of non-volatile memory devices include conventional flash electronically erasable programmable read-only memories (EEPROMs). A typical non-volatile memory device includes an array of NAND gates. A conventional NAND gate typically has a dual gate structure which includes a thin tunnel oxide layer between two field oxide portions on a substrate, a polysilicon floating gate which comprises a first polysilicon (POLY-1) layer on the tunnel oxide layer, a dielectric stack on the floating gate, and a polysilicon control gate which comprises a second polysilicon (POLY-2) layer on the dielectric stack. The dual gate structure of a conventional NAND flash memory device with POLY-1 and POLY-2 layers separated by an interpolysilicon dielectric stack is known to a person skilled in the art.
FIG. 1 shows a typical circuit diagram of an array of NAND flash memory gates 2a, 2b, 4a, 4b, 6a and 6b as part of a non-volatile memory device on a semiconductor integrated circuit. The NAND gates 2a, 2b, 4a, 4b, 6a and 6b each have a dual gate structure with a polysilicon floating gate and a polysilicon control gate. The NAND gates 2a and 2b, which are connected together in series in column 2 in the array of NAND gates, are connected to a select drain gate 2c and a select source gate 2d in the same column 2. In a similar manner, the NAND gates 4a and 4b in column 4 are connected to a select drain gate 4c and a select source gate 4d in the same column 4.
The NAND gates 2a and 4a are arranged in the same row with a control line 7 connected to the control gates of the NAND gates 2a and 4a. Similarly, the NAND gates 2b and 4b are arranged in the same row, with their control gates connected to another control line 8. The select drain gates 2c, 4c, 6c and the select source gates 2d, 4d, 6d each have only one polysilicon gate layer which can be implemented on a substrate as a first polysilicon (POLY-1) layer. The select drain gates 2c, 4c and 6c are connected in the same row by a single strip of POLY-1 layer across the row of select drain gates 2c, 4c and 6c. In a similar manner, the select source gates 2d, 4d and 6d are connected together by a single strip of POLY-1 layer 12 across the row of select source gates 2d, 4d and 6d.
FIG. 2 is a simplified plan view of the NAND flash memory of FIG. 1 implemented on a semiconductor substrate 14. A first polysilicon (POLY-1) layer 16 is deposited on the substrate 14 and then etched to form the pattern as shown in FIG. 2. A photoresist mask 18 is patterned and provided on the POLY-1 layer 16 before the POLY-1 layer 16 is etched by using a conventional etch such as a plasma etch to form the pattern as shown in FIG. 2. After the etching of the POLY-1 layer 16, channel stop implant windows 21 and 23 are formed on top of field oxide regions 20 and 22, respectively. For the purpose of illustration only, FIG. 2 shows the locations of the floating gates of the NAND gates 2a, 2b, 2c, 4a, 4b, 4c, 6a, 6b and 6c disposed along the respective column strips 2, 4 and 6 after the depositing and etching of a second polysilicon (POLY-2) layer (not shown) are completed. Further, FIG. 2 illustrates a row strip 10 which is connected across the select drain gates 2c, 4c and 6c, and another row strip 12 which is connected across the select source gates 2d, 4d and 6d.
Prior to the step of depositing the POLY-1 layer 16 on the substrate 14, an oxide layer is provided on the substrate 14. A cross-sectional view of the NAND flash memory of FIG. 2 obtained by a sectional cut along the sectional line 101a-101b is shown in FIG. 3, with core field oxide regions 20 and 22 disposed between adjacent POLY-1 layer strips 2, 4 and 6, which are also called bit lines in a flash memory device. The NAND flash memory also includes very thin tunnel oxide layers 24, 26 and 28 beneath the POLY-1 layer 16 of the NAND gate strips 2, 4 and 6, respectively. The core field oxide regions 20 and 22 between the NAND gate strips 2, 4 and 6 are usually much thicker than the tunnel oxide layers 24, 26 and 28. The fabrication of the silicon substrate 14, the core field oxide regions 20 and 22, the tunnel oxide layers 24, 26 and 28, and the POLY-1 layer 16 is conventional and known to a person skilled in the art.
Referring back to the plan view of FIG. 2, the field oxide regions 20 and 22 are shown as core field oxide strips 20 and 22, which are exposed through the respective channel stop implant windows 21 and 23. The control lines 7 and 8, also called word lines, which are shown as strips indicated by dashed lines, have not yet been formed on the NAND gate structure during the patterning and etching of the POLY-1 layer 16, and are shown for the purpose of illustration only. The areas in which the control lines 7 and 8 overlap the vertical strips 2, 4 and 6 of the POLY-1 layer 16 in the plan view of FIG. 2 define the control gates and the floating gates, respectively, of the NAND gates 2a, 4a, 6a, 2b, 4b and 6b. The control lines 7 and 8 may be provided by depositing, patterning and etching a second polysilicon (POLY-2) layer (not shown) after providing an interpolysilicon dielectric structure such as an oxide-nitride-oxide (ONO) trilayer structure (not shown) on the POLY-1 layer 16. However, since the select drain gates 2c, 4c and 6c and the select source gates 2d, 4d and 6d are formed by a single polysilicon (POLY-1) layer 16, no control lines are provided on top of the select drain gate strip 10 and the select source gate strip 12.
The core field oxide region 20 extends beneath the select drain gate strip 10 and the select source gate strip 12 as select drain gate and select source gate transistor field oxide regions 30 and 32, respectively. Similarly, the core field oxide region 22 extends under the select drain gate strip 10 and the select source gate strip 12 as field oxide regions 34 and 36, respectively. The edges 31, 33 and 34, 36 of the respective channel stop implant windows 21 and 23 are located adjacent the respective edges 38 and 44 of the select drain gate strip 10 and the select source gate strip 12. The edge 38 of the select drain gate strip 10 is separated by a narrow spacing 40 from the edge 31 of the channel stop implant window 21 which exposes the core field oxide region 20. Another spacing 42 exists between the edge 44 of the select source gate strip 12 and the edge 33 of the channel stop implant window 21 which exposes the core field oxide region 20.
The dimensions of the NAND non-volatile memory devices have been aggressively shrunk down in recent years in order to provide larger scale integration. When the dimension of the device is shrunk down to a very small size, the channel stop implant window is subjected to a "rounding affect" which enlarges the effective spacing between the edge 38 of the select drain gate strip 10 and the channel stop implant window 21 relative to the size of the select drain gate strip 10 and the core field oxide region 20. Attempts have been made to reduce the spacing 40 between the channel stop implant window 21 and the edge 38 of the select drain gate strip 10. The rounding of the edge 31 of the channel stop implant window 21 is shown in the enlarged plan view of FIG. 4. The spacing 40 may be further decreased to reduce the effective spacing due to the rounding effect. However, a disadvantage of reducing the spacing 40 between the channel stop implant window 21 and the edge 38 of the select drain gate strip 10 is that a part of the select drain gate strip 10 of the POLY-1 layer 16 may be etched if there is a misalignment between the core field oxide region 20 and the select drain gate strip 10 or when the spacing 40 is reduced to a very small size approaching zero.
FIG. 5 shows an enlarged plan view of a NAND flash memory device in which a misalignment between the core field oxide region 20 and the select drain gate strip 10 results in an overlapping of the channel stop implant window 21 and the select drain gate strip 10. In this case, a portion 46 of the select drain gate strip 10 is etched because the channel stop implant window 21 overlaps the edge 38 of the select drain gate strip 10 and "eats into" the portion 46 of the select drain gate strip 10. Since the width of the select drain gate strip 10 is reduced by the portion 46, which has been etched away, a high resistance is introduced by the narrower segment of the strip 10 of the POLY-1 layer 16 between the adjacent select drain gates 2c and 4c. Decreasing the spacing between the channel stop implant window 21 and the select drain gate strip 10 thus may cause process control problems resulting in a high resistance, which is undesirable, between the select drain gates 2c and 4c on the POLY-1 layer 16. Therefore, there is a need for a method of fabricating a NAND non-volatile memory device without the necessity of aggressively shrinking the spacing between the channel stop implant window and the select drain gate strip such that the risk of undesirably etching at least a portion of the select drain gate strip can be avoided.
Another problem associated with a conventional NAND non-volatile memory device is that the field region under the select drain gates may undesirably "turn on" due to a low field turn-on voltage which results from a low doping concentration under the select drain gate strip in a conventional NAND non-volatile memory device. When a field turn-on occurs, an excess leakage current will flow between the bit lines, thereby causing product failure. The field turn-on may occur even if the spacing between the channel stop implant window and the edge of the select drain gate strip is small enough and even if the problem of misalignment due to process control variations is avoided. Therefore, there is a further need to increase the field threshold voltage of the select drain gates such that a field turn-on can be avoided under normal operating conditions.